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Automotive Solution CoCs

This System-on-Chip family, based on Arm® Cortex® processors, combine a broad level of integration on a single chip together with a multicore platform offering highly flexible designs of user interfaces in 3D and/or 2D for a range of applications.

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Features SC1711AH5 SC1701BK3-100 SC1701BH5-100 SC1701BK3-200 SC1701BH5-200 SC1701BK5-300
Chip
Target market Automotive
Targeted applications Remote Displays, Instrument Cluster, Head-up Display Remote Displays (High Res.), Instrument Cluster, Head-up Display
Qualification AEC-Q100
Samples Mass production Development Development Development Development Development
Core Performance
Socionext Command Sequencer Version V 2.0 V 3.0
Clock (automotive variant) 160 MHz 300 MHz 200 MHz 300 MHz 200 MHz
Spread Spectrum Clock Modulation Yes
Memory
Embedded SRAM 128 kB 256 kB (9 kB ECC)
Embedded Flash 56 kB 128 kB
External Flash Interface SPI Interface, legacy, dual and quad mode
Graphics cores
2D GPU Socionext SEERIS® MVL 2D GPU core Socionext SEERIS® MVL3 2D GPU core
Internal TCON Yes
Processing CLUT, Matrix, Dither, Sprites, α blending CLUT, Dither, α blending, Up/down-scale, Histogram CLUT, Dither, α blending, Histogram
VESA DSC compression no Yes, Version 1.2 (2:1/3:1) no
Max. Pixel Clock 144 MHz 2 x 266 MHz / 1 x 533 MHz 160 MHz 2 x 266 MHz / 1 x 533 MHz 160 MHz 140 MHz
Color Resolution 8 Bit / channel 10 Bit / channel
Color Formats RGBA(all formats), Indexed, Grey scale, Compressed RGBA
SigatureUnit(s) 4 16 or 2 x 8 16 16 or 2 x 8 16 8
Safety Layer no Yes
Display
Number of parallel display controllers 1 2 1 2 1
Max resolution per output 1280x480 @60fps (24bit) 1 x 3840x2160 @60fps (30bit)
2 x 2560x1600 @60fps (30bit)
1920x1080 @60fps (30bit) 1 x 3840x2160 @60fps (30bit)
2 x 2560x1600 @60fps (30bit)
1920x1200 @60fps (30bit) 1920x1080 @60fps (30bit)
Display Port output TCON-RSDS, TTL,
dual LVDS (OpenLDI)
Dual TCON-RSDS, 2 x 6 pair miniLVDS, TTL,
2 x dual LVDS (OpenLDI)
RSDS, 6 pair miniLVDS, TTL,
dual LVDS (OpenLDI)
Dual TCON-RSDS, 2 x 6 pair miniLVDS, TTL,
2 x dual LVDS (OpenLDI)
RSDS, 6 pair miniLVDS, TTL,
dual LVDS (OpenLDI)
RSDS, TTL,
dual LVDS (OpenLDI)
APIX Interface
APIX® PHY APIX®2 APIX®3 No
Daisy-Chain support No Yes (requires external Tx) No No
Maximum Bandwidth 1 GBit/s 12 Gbit/s 6 Gbit/s  -
HDCP support No HDCP 1.4 No
Number of video channels 1x 2x 1x No
Support for Ethernet over APIX Yes No
Ethernet Endpoints 2 (but only 1 addressable during runtime) 2 (simultaneously addressable through arbiter during runtime) No
Standard I/O
UART 1x 2x
I²C 2x
I²S 1x 2x 1x
SPI 4x 2x HS-SPI or 1x HS-SPI + 4x SPI
Lin 1x (shared with UART) 2x (shared with UART)
ADC 16x 10x 8x 10x 8x
SMC 6x
GPIO max. 110 max. 139 max. 133 max. 139 max. 133
PWM 16x
External Interrupt Input 8x
Package
Package Type (Automotive) EP - LQFP HS - BGA EP - LQFP HS - BGA EP - LQFP
Number of pins 176 319 216 319 216
Lead/ Ball Pitch 0.4 mm 1 mm 0.4 mm 1 mm 0.4 mm
Package Size 20x20 mm 23x23 mm 24x24 mm 23x23 mm 24x24 mm
Temperature Range Ta -40 to +105C

ARM® Cortex®-A9 Single Core Processors, 2D Engine SEERIS™, 3D OpenGL® ES 2.0 GPU, four VideoCapture Units and three Display Controllers Including APIX2®

Designed for cost sensitive markets the ARM® Cortex®-A9 Single Core Processor SoCs offer low power consumption on highly integrated single chip architectures. The MB86R1x Family combines a high-performance CPU with four video inputs and up to three display outputs, enabling high-speed image processing of video data I/O from these interfaces.

The combination of Socionext’s 2D Engine SEERIS™ and the in-house developed 3D OpenGL® ES 2.0 Engine, means highly flexible and powerful graphics processing is possible. Tailored for embedded use, SEERIS™ allows the combination of graphics, such as videos, pictures, icons or 3D OpenGL® ES 2.0 graphics, to be rendered by the GPU. This particular combination of graphics processing can be adapted for different applications.

The essential key feature of MB86R12 is its Inova Semiconductors’ high-speed APIX2® (Automotive/Advanced Pixel Link) GBit/s interface. This point-to-point connectivity transmits uncompressed and resolution independent pixel data over long distances for cameras and displays. The APIX® technology consists of a downstream link and an optional upstream link. Please refer to the Graphic Display Controller (GDC) family supporting the APIX receiver for remote displays units.

Multiple performance and package options are available.

Key Features

  • Single ARM® Cortex™ A9 Core
  • ARM® Neon™ SIMD Engine
  • 3D Engine (OpenGL® ES 2.0) ‘Ruby’
  • 2D Engine SEERIS™
  • DDR2-400/533/800 and DDR3-800/1066, x32 bus width, 1GB
  • 3 Display controllers (RSDS, RGB, APIX2®)
  • 4 Independent Video Capture Units (APIX2®)
  • Standard I/O: UART, SPI, USB etc.
  • Automotive I/F: CAN, MediaLB®

Product Options

  • MB86R11FBH-GSE1
  • MB86R12FBH-GSE1
  • MB86R13FBH-GSE1

Factsheet: MB86R1x - ARM® Core Based Processors

Cost sensitive MB86R1x Graphics SoC Series for highly integrated single chip architectures


How to Buy

ARM® Cortex®-A9 Dual Core Processors, 2D Engine SEERIS™, 3D OpenGL® ES 2.0 GPU, six Video Capture Units and three Display Controller

The ARM® Cortex®-A9 Dual Core Processors SoCs are designed for mid range high performance embedded applications. The MB86R2x Family combines the high-performance MPCore™ with six video inputs and up to three display outputs, enabling the high-speed image processing of video data I/O from these interfaces.

The combination of Socionext’s 2D Engine SEERIS™ and the PowerVR™ SGX 3D OpenGL® ES 2.0 allows highly flexible powerful graphics processing. Tailored for embedded use SEERIS™ allows a combination of graphics such as videos, pictures, icons or 3D OpenGL® ES 2.0 graphics to be rendered by the GPU. This particular combination of graphics processing can be adapted to different applications. The warping-on-the-fly feature of SEERIS™ is designed for Head-up displays which require images to be corrected immediately and reduces the overall required system performance.

A significant increase in memory bus performance and memory interfaces is supported by x64 DDR3/3L bus width. Enhanced scalability was achieved due to identical pin and package compatibility. Please refer to the Graphic Display Controller (GDC) product line. The MB86R91BGL-GSE1 used as a communication and video bridge, is designed to connect directly to the three display outputs of the MB86R2x. The essential key feature of MB86R91 is its integrated Inova Semiconductors’ high-speed APIX2® (Automotive/Advanced Pixel Link) GBit/s transmitter and receiver interfaces.

Key Features

  • Dual ARM® Cortex® A9 MPCore™ (2x 533MHz)
  • ARM® Neon™ SIMD Engine
  • 3D Engine (OpenGL® ES 2.0) ‘PowerVR™ SGX543-MP1’
  • 2D Engine SEERIS™
  • Warping-on-the-fly
  • DDR3/3L-800/1066, x16, x32, x64 bus width
  • 3 Display controllers (FPD, RGB)
  • 6 Independent Video Capture Units
  • Standard I/O: UART, SPI, USB, Ethernet AVB etc.
  • Automotive I/F: CAN, MediaLB® (3-Pin)

Product Options

  • MB86R24RBB-GSE1

All-in-One: Remote Head-up, Instrument Cluster and Operating Panel

360° Wrap-Around View System

Factsheet: MB86R2x – ARM® Core Based Processors

Third-Generation Graphics SoC has high performance CPU/GPU.


How to Buy

SC1810x – ARM® Core Based Processors

The SC1810 features state-of-the-art functions and performance for in-vehicle graphics display applications such as digital clusters, central HMI and surround-view-systems.

In addition to its high resolution graphics capability with improved 3-D image processing performance which is five times more than that of the company’s previous products, the SoC is also capable of handling 6 channels Full HD video inputs and 3 channels of Full HD display outputs, enabling variety of input and output controls.

The SoC realizes "Integrated HMI (Human Machine Interface) system" which manages various information from inside and outside the car and controls multiple displays, with higher definition and image quality.

Furthermore, the SC1810 is equipped with a proprietary "Vision Processor Unit (VPU)", which is compliant with the computer vision API OpenVX, developed by the standardization organization Khronos Group.

The SC1810 VPU includes the world's first OpenVX compliant hardware accelerator, as well as programmable data parallel accelerator, enabling advanced image recognition and other advanced functions at high speed and low power consumption.

Application Example

Key Features

  • Quad ARM® Cortex™ A9 MPCore™
  • ARM® Neon™ SIMD Engine
  • 3D Engine (OpenGL® ES 3.1) ‘POWERVR 8XE
  • Socionext SEERIS Capture/Graphics/Display Engines
  • Socionext Vision Processor
  • DDR3-1866; DDR3L-1600, 16/32/64 bus width
  • 3 Independent Display controller
  • 6 Independent Video Capture Units
  • Multi-format Decoder Full-HD: 6x30fps or 2x60fps
  • Multi-format Encoder Full-HD: 2x60fps
  • Motion JPEG Decoder Full-HD 6x30fps
  • Standard I/O: UART, SPI, USB, Ethernet AVB etc.
  • Automotive I/F: MediaLB® (3-/6-Pin), CAN
  • 28nm CMOS; FCBGA-1024; 0.8 pitch


Product Options

  • AR3-134 (SD support)
  • AR3-113 (HD support)
  • AR3-103 (Full feature)

Factsheet: SC1810x – ARM® Core Based Processors

Next-Gen Automotive & Industrial HMI Solutions powered by the SC1810x Graphics SoC Series


How to Buy

ARM® Cortex®-A5 Quad Core Processors, 2D Engine, 3D OpenGL® ES 2.0 GPU, Multi-format Digital Decoder and Encoder

The MB8AL203x is a highly integrated HD Multi-format digital decoder and encoder designed to meet the needs of tomorrow’s hybrid set-top-boxes, home networking solutions and automotive systems. It features CI+ and embedded CAS for advanced security.

The high-performance Quad ARM® Cortex®-A5 MPCore™ CPU, 2D graphics engine and PowerVR™ SGX 3D OpenGL® ES 2.0 are matched to one another for harmonized system architecture. The chip is designed to fulfill the latest advanced security specifications.

The chip supports up to 1080p HD encode/decode. This high performance multi-media processing allows decoding of various formats including the latest compression standard HEVC (H.265) and output of two streams in parallel in HD resolution. One of the essential key features is MPEG layer 1/2, MP3, HE-AAC and Dolby Digital audio decoding which are fully programmable and easy to extend.



Key Features

  • Quad ARM® Cortex™ A5 MPCore ™
  • ARM® Neon™ SIMD Engine
  • 3D Engine (OpenGL® ES 2.0)
    ‘POWERVR SGX531-MP1, 2D Engine
  • DDR3-1080, 2 x16, bus width
  • 2 Display controller
  • 2 Video Capture Units
  • Multi-format HD Video Decoder (incl. H.265)
  • HD Video Encoder
  • 4 Audio Capture
  • Standard I/O: UART, SPI, USB, Ethernet etc.
  • Cipher engine with AES/DES, hash and
    DTCP accelerator, secure boot
  • Automotive I/F: MediaLB® (3-/6-Pin)

Product Options

  • MB8AL2039B MH

Factsheet: MB8AL203x – Multi-format HD Decoder LSI

Socionext’s MB8AL203x is a highly integrated HD multi-format digital TV decoder and encoder designed to meet the future needs of set-top boxes, digital signage, home networking and in-car infotainment.


How to Buy
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