Video Codec

Video Codec Pictures technology

The amount of video data being transferred through the world´s networks is increasing dramatically, driven by both technical innovation and the way that users wish to experience video information.

Here at Socionext we are the link between ´source´ which is the video authoring process, and ´destination´ which is the image display process.

We offer the World´s most advanced video codec technology to ensure image transmission of the highest quality. This is backed up by a proven track record and expertise in video systems and broadcasting, and our expertise in graphic solutions, thereby enabling full end-to-end solutions for video transmission and display.


Product Lineup

Roadmap Product Lineup

Products

SC2M50 provides video encoding and decoding that support HEVC/H.265 standard. SC2M50 is a slave type codec IC controlled by host CPU via PCIe interface.


Features

  • 4K/60p HEVC/H.265 real-time encoding/decoding
  • HEVC encoding algorithm supporting HDR(High Dynamic Range) Video
  • Low power consumption(3.5W at 4K/60p HEVC encoding) enables battery powered system

Applications

  • IP video distribution
  • Wireless video transmission
  • Medical
  • Signage

Block Diagramm

Block Diagram SC2M50

Specifications

Video encoding HEVC Main, Main10, Format Range Extensions
(4:2:2 / 4:2:0, 8/10bit, up to 4K 60p)
decoding HEVC Main, Main10, Format Range Extensions
(4:2:2 / 4:2:0, 8/10bit, up to 4K 60p)
Audio encoding MPEG1 Audio Layer2
MPEG2 AAC-LC
SMPTE302M (LPCM)
decoding MPEG1 Audio Layer2
MPEG2 AAC-LC
SMPTE302M (LPCM)
Stream input / output TS input x 1
TS output x 1
Video input / output 20bit Parallel I/F input x 4, output x 4
YUV 4:2:2 10bit up to 4K 60p
SMPTE-435(Square Division),
SMPTE ST2036-3 (2-Sample Interleave Division),
SMPTE 424M (3G-SDI),
SMPTE 274M, SMPTE 292M (HD-SDI),
SMPTE 259M-C (SD-SDI)
Audio input / output I2S x 2
Peripheral interface PCI express Gen 2.0 (4 lanes, Max payload size 512 byte)
USB 2.0 Device x 1
UART x 4
I2C x 3
SPI x 2
GPIO x 64
Memory interface Serial flash interface HSSPI x 1
LPDDR4 2400Mbps 16bits x 6 (maximum)
Image processing Video overlay (option)
Technology 28nm Process / 1,361 pin FCBGA 25?? x 25mm
Power Consumption 3.5W (Typical)

Product catalog

pdf

AD04-00117-1E.pdf
Size: 0.614 Megabyte | Date: 30.07.2019 18:06

“MB86M30” provides video and audio encoding, decoding, and transcoding with supporting HEVC/H.265, AVC/H.264 and MPEG2 standard.
MB86M30 is slave type device controlled by host CPU via PCIe interface.


Features

  • 4K/60p HEVC/H.265 or AVC/H.264 real-time encoding/decoding
  • 4K/60p HEVC/H.265 encoding with 10ms ultra low latency (Option)
  • HEVC encoding algorithm supporting HDR (High Dynamic Range) Video
  • Low power consumption (6.3W at 4K/60p HEVC encoding) and embedding four DRAMs in package enable high density in the system

Applications

  • Broadcasting
  • IP Video distribution
  • Medical
  • Signage

Block Diagramm

Block Diagramm

Specifications

Video Encoding HEVC/H.265 4:2:2 10bit (up to 4096 x 2160p60)
AVC/H.264 4:2:2 10bit (up to 2160p60)
MPEG2 4:2:0 8bit (up to 1080i59.94, 1080p30)
Ultra Low Latency Encoding *1 HEVC/H.265 4:2:2 10bit (up to 4096 x 2160p60)
Latency: 10ms
Decoding *2 HEVC/H.265 4:2:2 10bit (up to 4096 x 2160p60)
AVC/H.264 4:2:2 10bit (up to 2160p60)
MPEG2 4:2:0 8bit (up to 1080i59.94, 1080p30)
Transcoding *3 HEVC to HEVC, H.264 to HEVC, MPEG2 to HEVC, etc.
Pre-Processing De-Interlacing, Scaling, Filtering, Video overlay
Multiple channel operation Up to 4ch @HEVC/H.265 encoding, 1080p60
HDR ready  
Audio Encoding LPCM, AAC-LC, MPEG1-Layer2
Decoding LPCM, AAC-LC, MPEG1-Layer2
Pass through  
Stream processing TS MUX Up to 4ch
TS DEMUX Up to 4ch
Interface Control PCIe 2.0
Stream PCIe 2.0, TS-Serial Input x 4ch, TS-Serial Output x 4ch
Video PCIe 2.0, Video Parallel Input x 4ch, Video Parallel Output x 4ch
Audio I2S Input x 4 stereo pair, I2S Output x 4 stereo pair
System Internal Memory LPDDR4-2400 8Gbits x 4pcs
External Memory LPDDR4-2400 (16bit x 2ch) x 2pcs
Boot Device SPI Flash
Package FCBGA 74.5mm x 47.5mm

Factsheet: MB86M30 – 4K/60p HEVC Multi-Format Codec

pdf

MB86M30_AD04-00110-1E.pdf
Size: 0.292 Megabyte | Date: 28.12.2017 12:08

“MB86M31” provides H.265/HEVC 4K60p real-time encoding by single chip. The MB86M31 is slave type device controlled by host CPU via PCIe interface.


Features

  • HW base H.265/HEVC 4K60p real-time video encoder
  • Support Main 4:2:2 10 profile necessary for broadcasting applications
  • Support multi-channel video encoding: 1080p60 4ch, 720p60 8ch, 480p 16ch
  • Low power consumption

Applications

  • Broadcasting
  • Video capture
  • Medical

Block Diagram

Block Diagram

Specifications

Video Encoding H.265/HEVC Main, Main 10, Main 4:2:2 10 profile
Multi channel encoding: 4K60p 1ch,
1080p60 4ch, 720p60 8ch, 480p 16ch
Interface   Control PCIe Gen 2.0
Peripheral PCIe Gen 2.0 (4 lanes x2, 5.0 GT/s, Max payload size 1024 Bytes, Lane reversal supported)
UART (4 channels)
I2C (2 channels)
SPI (1 channel)
GPIO (64 pin)
Video 20bit parallel interface (4 channels) support YUV4:2:2 10bit up to 4K
Support embedded sync (CEA-861)
System   CPU ARM Cortex-A7 400MHz single core
Memory I/F DDR3 SDRAM 1333Mbps (16bitx2, 4channels)
Boot Device Serial flash, Nor Flash
Physical   Power supply Internal Logic: 1.2V, Analog: 1.2V/3.3V, I/O: 1.5V / 1.8V
Operating temperature Ta = 0 to 70°
Package FCBGA-1764 (35mm x 35mm, 0.8mm pitch)

Deliverables for system development

Evaluation board

  • PCIe card form
  • Support 4ch 3G-SDI input

Software Development Kit

  • Including Host CPU driver, sample application (Source code)

Documentation

  • MB86M31 datasheet, evaluation board schematic, board design database
  • Host CPU driver, Sample application software, Control command document

Factsheet: MB86M31 – H.265/HEVC 4K/60p Real-time Encoder

pdf

MB86M31.pdf
Size: 0.29 Megabyte | Date: 28.12.2017 12:08

The MB8AL203x is a highly integrated HD Multi-format digital TV decoder and encoder designed to meet the needs of tomorrow’s hybrid set-top-boxes, digital signage, home networking solutions and in-car infotainment systems also featuring CI+ and embedded advanced security. The LSI supports up to 1080p HD encode/decode. The high performance multi-media processing allows decoding of various formats including the latest compression standard HEVC and outputting two streams parallel in HD resolution.

 MB8AL203x - highly integrated HD Multi-format digital TV decoder

Features

  • Quad ARM® CortexTM A5 MPCore TM incl. NeonTM SIMD Engine
  • Multi-format HD Video Decoder incl. HEVC
  • HD H.264 Video Encoder
  • 3D Engine (OpenGL® ES 2.0) ‘POWERVR SGX531-MP1’, 2D Engine
  • Cipher engine with AES/DES, hash and DTCP accelerator, OTP, secure boot
  • Power consumption 2.0W (typ)
  • Automotive
    • Temp range -40C to +85C
    • I/F: MediaLB® (3-/6-Pin)
    • AEC-Q100

Block Diagram

Block Diagramm

Specifications

System

  • CPU: quad-core CortexA5 @ 396MHz, NEON, 32kB I$/D$ cache
  • Memory: 2x 16-bit DDR3-1080 SDRAM interface
  • Boot devices: NOR, NAND, eMMC4.41 or serial flash
  • Standby: Power Island for deep power down

Video/Audio

  • 4x Transport stream demultiplexer incl. descramblers for DVB
  • CSA 3/2.1/1.0, AES/(T)DES, Multi-2, 4x TS input, 2x TS output
  • Cipher engine with AES/DES, hash and DTCP accelerator
  • Secure boot, control word protection, OTP & memory encryption
  • Multi-format video decoder for HEVC L4.1, H.264 L4.2 HP, MPEG-2 MP@HL, MPEG 4 ASP L5, AVS Jizhun Profile, VP 6/7/8, VC-1 AP L3, RealVideo® 8/9/10, DivX® 3/4/5/6, H.263, Sorenson Spark
  • H.264 video encoder up to HD resolution (depend on frame rate)
  • JPEG decoder/encoder
  • 2 independent video outputs. Layers (flexible order): 2x backplane, 2x video, 2x cursor, 5x OSD (up to true-color in HD resolution, two layer scalable with flicker fixer), YCrCb/RGB color space
  • 3D graphic engine (Power VR SGX531); separate 2D bit blitter
  • Motion adaptive HD de-interlacer
  • PAL/NTSC/SECAM encoder incl. cross color, luminance filters, Teletext, WSS, CC, VBID insertion

Interfaces

  • HDMI Link and PHY with HDCP and CEC controller
  • 16bit digital video incl. SAV/EAV: 1x Input/1x Output (compliant to SMPTE 296M/274M)
  • 24bit dig. RGB (EIA/CAE-861 compliant), 2x out or 1x out + 1x in
  • ITU-R 656 video: 2x Input/1x Output
  • 4x analog video DACs for YPrPb/RGB, YC and CVBS
  • Stereo audio DACs, I2S: 4x input and 5x output, 1x SPDIF output
  • 2x USB 2.0 with 16 end-points incl. PHY (host or device)
  • Eth. 10/100/1000 Base-T GMAC (RGMII/RMII/MII), IEEE 1588
  • Universal processor interface (NAND/NOR, DVB-CI/CI+, IDE, ATA)
  • Universal slave interface (CI, IDE, ATA)
  • MediaLB, 6-pin and 3-pin interface (MOST25/50/150)
  • 128x Shared GPIO, 2x UART, 2x Smart Card, 2x I2C, 4x PWM, IR Rx, 2xSPI Master/Slave, 2x SDIO, 4x 7-segment LED, 8x Key Input
  • 4 channels Analog-Digital Converter (10bit)

Package/Technology

  • PBGA-484 Package/Fujitsu CMOS 55nm technology
  • Operating Temperature range: -40 to +85, AEC-Q100
  • Supply: 1.2V core, 1.5V DDR, 1.8V/3.3V I/O (some are 5V tolerant input) • Power Consumption: 2W (typ)

Factsheet: MB8AL203x Multi-format HD Decoder LSI

pdf

MB8AL203x.pdf
Size: 0.381 Megabyte | Date: 28.12.2017 12:10

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