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Synopsys Accelerates Multi-Die Designs with Industry's First Complete HBM3 IP and Verification Solutions

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HBM3 IP Solution Delivers Maximum Memory Bandwidth of 921 GB/s for High-Performance Computing, AI, and Graphics SoCs

"Socionext, a global leader in SoC solutions, together with Synopsys, an industry-leading partner, provide comprehensive solutions to our customers across a wide range of markets," said Yutaka Hayashi, vice president of Data Center & Networking Business Unit at Socionext. "Our recent collaboration with Synopsys, leveraging Synopsys' HBM2E IP on 5-nm process and integrated full-system multi-die design platform, will extend to include the new DesignWare HBM3 IP and verification solutions. As a result, our customers can achieve higher memory performance and capacity in SoCs requiring the upcoming HBM3 specification."


Highlights of this Announcement:

  • The DesignWare HBM3 Controller, PHY, and Verification IP reduces integration risk and maximizes memory performance in 2.5D multi-die systems
  • Low-latency HBM3 Controller with flexible configuration options enhance memory bandwidth
  • Pre-hardened or configurable HBM3 PHY in 5-nm process operates at 7200 Mbps for up to 2X the data rate and improves power efficiency by up to 60% compared to HBM2E
  • Verification IP and memory models for ZeBu and HAPS offer an end-to-end solution for rapid verification closure from IP to SoC
  • Synopsys' 3DIC Compiler, an integrated multi-die design and analysis platform, provides a comprehensive HBM3 auto-routing solution for rapid and robust design development

Read the full announcement here.

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